1. Field of the Invention
The present invention relates to a serial interface circuit for use when a central processing unit (CPU) accesses a peripheral circuit, and more particularly, to a reduction of the CPU overhead when a CPU accesses a peripheral circuit.
2. Description of the Related Art
The use of the finer semiconductor process leads to an increase of the transistor off-leak current, thereby increasing the consumption current of a large-scale integrated (LSI) circuit in a standby state, where clock and input/output operations stop, to a too high level to ignore. The reduction of the consumption current is a big issue especially for a portable device taking power from a battery. One of the most effective methods for reducing the consumption current in a standby state is to shut off power to the LSI circuit.
In a case of an LSI circuit which shuts off the entire circuit when powering off, there is no problem to use a usual shut-off procedure and a usual power-on procedure. In a case of an LSI circuit which shuts off a part of the circuit when powering off, such as an LSI circuit including an internal clock function, the LSI circuit must be divided into a backup area portion which must be always powered and a power-off area portion which can be powered off, and must have a backup mode, in which the power-off area portion is powered off and the backup area portion is not powered off in a standby state.
The LSI circuit including both the backup area portion and the power-off area portion tends to have a reduced withstand voltage due to the finer semiconductor process and cause a gate oxide film to be broken down due to a current flowing into a transistor circuit from a different power supply. Therefore, a protection device against such electrostatic breakdown and latch-ups must be provided on each signal line of the interface. As the number of the signal lines increases, an area occupied by the protection devices provided on the individual signal lines has become too large to ignore.
One solution to the above problem is to change the interface between the backup area portion and the power-off area portion from parallel to serial, suppressing an increase in the number of the signal lines and consequently reducing an area occupied by the protection devices.
FIG. 1 is a diagram showing a configuration of a part of an LSI circuit including a conventional serial interface circuit. The LSI circuit includes a power-off area portion PO including a CPU 1, as shown in the left half of FIG. 1, and a backup area portion BU including an internal clock (not shown) and other components, as shown in the right half of FIG. 1.
Referring to FIG. 1, the power-off area portion PO includes a shift register (SR) 11 for use when 32-bit data are serially transferred to/from the backup area portion BU, a shift register (SR) 12 for use when a 2-bit address specifying a register in the backup area portion BU is serially transferred, and a shift register (SR) 13 for use when a 1-bit control signal specifying a read operation or a write operation is transferred to the backup area portion BU. The power-off area portion PO also includes a first control block 14, a mode control circuit 71, and protection devices PD. The shift registers 11, 12 and 13 are connected in series and send/receive a 35-bit signal to/from the backup area portion BU serially in synchronization with a shift clock SCK sent from the first control block 14.
The shift register 11 is configured to perform parallel transfer of read data RD and write data WD to/from a system bus 2 connected to the CPU 1. The shift register 12 is configured to allow parallel input of an address signal AD from the system bus 2. The shift register 13 receives a control signal W/R for specifying a read operation or a write operation from the first control block 14, and holds the control signal W/R therein.
The first control block 14 controls the input/output of parallel data to/from the shift registers 11, 12 and 13 and a serial data shift in accordance with the control signal W/R, an operation enable signal EN, a system clock CLK and other signals sent from the CPU 1 through the system bus 2. Further, the first control block 14 outputs an operation enable signal REN and a clock signal RCK to the backup area portion BU in accordance with the control signal W/R, the operation enable signal EN, the system clock CLK and other signals.
Referring to FIG. 1, the backup area portion BU includes shift registers (SR) 51, 52 and 53 which correspond to the shift registers 11, 12 and 13 in the power-off area portion PO respectively. The backup area portion BU also includes a selector (SEL) 54, a second control block 55 and a comparator (CMP) 62. The shift register 51 sends/receives 32-bit data to/from the power-off area portion PO, the shift register 52 sends/receives a 2-bit address to/from the power-off area portion PO, and the shift register 53 sends/receives a 1-bit control signal to/from the power-off area portion PO. The shift register 13 in the power-off area portion PO gives serial write data SWD transferred through a first signal line 25 to serial input ports of the shift registers 51, 52 and 53. Serial output ports of the shift registers 51, 52 and 53 are connected to an input port of the selector (SEL) 54. The output port of the shift register 53 is connected to the second control block 55.
The shift registers 51, 52 and 53 and the selector 54 are configured to perform serial data transfer to/from the power-off area portion PO in accordance with control signals output from the second control block 55. The second control block 55 receives the operation enable signal REN and the clock signal RCK from the first control block 14 in the power-off area portion PO and the control signal W/R supplied through the shift registers 13 and 53. The second control block 55 generates shift clocks C51, C52 and C53 for the shift registers 51, 52 and 53 in accordance with the operation enable signal REN, the clock signal RCK and the control signal W/R. The second control block 55 also outputs a selection signal S54 to the selector 54, a load signal L51 to the shift register 51 and other signals successively. Serial read data SRD selected and output from the selector 54 is sent to the shift register 11 in the power-off area portion PO through a second signal line 65.
Referring to FIG. 1, the backup area portion BU also includes four registers consisting of a clock register 56, a control register 57, a compare register 58 and a status register 59. The backup area portion BU further includes a selector (SEL) 60, a decoder (DEC) 61 and protection devices (PD). The four registers 56 to 59 can be specified from the power-off area portion PO by an address signal AD. The clock register 56 increments its value by one in accordance with a count signal CNT sent at intervals of one second, for instance. The control register 57 controls the start and stop of the operation of the clock register 56. The compare register 58 specifies such a predetermined value that an interrupt processing occurs when the clock register 56 reaches the predetermined value. Data held in the status register 59 indicates the operating status of the backup area portion BU.
Output ports of the registers 56 to 59 are connected to input ports of the selector 60. An output port of the selector 60 is connected to a parallel input port of the shift register 51. A parallel output port of the shift register 51 is connected to the input ports of the registers 56 to 59 in common. A parallel output port of the shift register 52 is connected to a selection terminal of the selector 60 and an input terminal of the decoder 61. When the decoder 61 receives an operation enable signal E61 from the second control block 55, the decoder 61 decodes an address AD output from the shift register 52 to control the write operation to the corresponding one of the registers 56 to 59.
The comparator 62 receives values of the clock register 56 and the compare register 58, and if these values are the same, the comparator 62 outputs an interrupt signal INT to the power-off area portion PO. Each of the first signal line 25, the second signal line 65 and other lines that connect the power-off area portion PO and the backup area portion BU have protection devices PD against electrostatic breakdown and latch-ups on the signal receiving side.
In the LSI circuit including the serial interface circuit as described above, when the CPU 1 reads the value of the clock register 56 in the backup area portion BU, the address assigned to the clock register 56 (e.g., binary “00”) is specified as the address signal AD, the control signal W/R is set to a low level, and the operation enable signal EN is set to a high level.
Then, the write data WD, the address signal AD and the control signal W/R on the system bus are taken into the shift registers 11, 12 and 13 respectively, in accordance with a load signal L11 output from the first control block 14 in the power-off area portion PO. At the same time, the first control block 14 outputs the operation enable signal REN and the clock signal RCK to the second control block 55 in the backup area portion BU.
The signals taken into the shift registers 11, 12 and 13 are shifted successively in synchronization with the shift clock SCK supplied from the first control block 14, and transferred to the backup area portion BU as the 35-bit serial write data SWD.
In accordance with the operation enable signal REN and the clock signal RCK, the second control block 55 in the backup area portion BU puts the control signal W/R into the shift register 53 in synchronization with the shift clock C53 and puts the address signal AD into the shift register 52 in synchronization with the shift clock C52. At this time, the control signal W/R that has already put into the shift register 13 is sent to the decoder 61 as the operation enable signal E61. In this case, since the control signal W/R is low, the operation of the decoder 61 is disabled. Since the address signal AD is “00”, the selector 60 selects the clock register 56 and performs parallel input of the count value of the clock register 56 to the shift register 51, in accordance with the load signal L51 output from the second control block 55. The second control block 55 outputs the selection signal S54 for selecting the shift register 51 to the selector 54 and the shift clock C51 to the shift register 51. Then, the value of the clock register 56 put in the shift register 51 is transferred to the power-off area portion PO as serial read data SRD.
When the value of the clock register 56 is shifted and input to the shift register 11 in the power-off area portion PO, serial data transfer between the power-off area portion PO and the backup area portion BU stops. Then, the CPU 1 can perform a parallel read of data held in the shift register 11 through the system bus 2. A similar technique is shown in the U.S. Pat. No. 6,260,086 publication.
With the serial interface circuit as described above, the CPU 1 must keep the operation enable signal EN high during the serial data transfer between the power-off area portion PO and the backup area portion BU, and must keep the control signal W/R low or high, depending on whether a read operation or a write operation is performed. Therefore, the CPU 1 cannot perform any other processing, and enters the standby state during the serial data transfer. The degrading of the throughput in the serial interface circuit due to a large CPU overhead is greater than that in the parallel interface circuit.